SystemVerilog parser using Tree-Sitter

[](https://symbiflow.github.io/summer-of-code)

:construction: Work In Progress :construction:

# Brief explanation

[Verilog](https://en.wikipedia.org/wiki/Verilog) / [SystemVerilog](https://en.wikipedia.org/wiki/SystemVerilog) is a major hardware description language used in FPGA and Chip design.
Tree-Sitter is an incremental parsing system for programming tools https://tree-sitter.github.io
https://github.com/tree-sitter/tree-sitter-verilog - is IEEE 1800-2017 compliant parser.
Included in SymbiFlow SystemVerilog test suit: https://symbiflow.github.io/sv-tests/
Used in Atom editor: https://github.blog/2018-10-31-atoms-new-parsing-system/
Via plugin: https://github.com/drom/atom-ide-eda

# Detailed Explanation

https://github.com/tree-sitter/tree-sitter-verilog/issues

# Further reading

:construction: Work In Progress :construction: