Create a Python library for generating VtR arch.xml files

# Create a Python library for generating [VtR arch.xml files](https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html)

# Brief explanation

Verilog to Routing uses XML files to describe the architecture in an FPGA. [This format is described in the Verilog to Routing docs](https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html). We need to regularly generate these XML files from Python, so it would be nice to have a good library for doing that.

## Expected results

A Python library for generating VtR arch.xml files easily.

Start by reading the linked VtR architecture reference to inventory the arch.xml structure and required elements. Define the library scope from that format, then verify that it can generate valid VtR architecture XML files from Python; no project files or tests are named in the issue.

Written by the indexing model from the issue text.