Verilog AST format

# Brief explanation

Open and Common format of Abstract Syntax Tree of Verilog program.

## Expected results

Tools ecosystem using the format.

# Detailed Explanation

Open HDL ecosystem needs more tools and libraries to deal with Verilog.
Common Abstract Syntax Tree data format will enable interoperabity.

Good collection of AST formats for different langages: https://astexplorer.net/

Set of core libraries:
* Verilog parser --> AST
* Verilog code generator <-- AST
* AST traversal, query and utility libraries

Good example of ecosystem enabled by AST format is ESTools:
* Parser : http://esprima.org
* Linter : https://eslint.org
* Compiler : https://babeljs.io
* Code coverage : https://istanbul.js.org
* Tool belt : https://github.com/estools

## Further reading

http://modularity.info/conference/2013/escodegen.html

Start by reviewing the proposed parser, code generator, AST traversal, query, and utility library roles, along with the linked AST format examples and ESTools ecosystem. Done would require a concrete, agreed Verilog AST format and an identified ecosystem of compatible tools; no repository files or tests are named.

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