Lowlevel LLVM-like language as HDL middle layer

Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will allow to add 1) targets easier 2) HDL frontends easier.

Criteria for selection:

- Do we expect it to have a human readable form? [BOTH]
- binary version
- a text version with extracted symbol table?
- more tops per file?
- Include?
- behavioural description / pure structural? [STRUCTURAL]
- process (Verilog like mux, reg... desc.) / netlist (mux, reg, ... descr. by instance) ?
- is [Chisel3 FIRRTL](https://github.com/freechipsproject/firrtl)/[Yosys RTLIL](http://www.clifford.at/yosys/files/yosys_manual.pdf) structural enough?
- Do we want it to be technology independent? [YES]
- Do we require parameters/preprocessor? [NO]
- Granularity gate / operator / process?
- Which has the priority in optimizations: loading time/analysis/modification/file size?
- Support for tristate signals?
- Support for strong/weak pull up/down?
- Clock domain as a wrapper around part of the netlist/ only as a input clk to registers?
- Support for synthesis related pragmas like multiclock path, clock domain crossing?

Needs of the particular projects:

[Chisel3](https://github.com/freechipsproject/chisel3/wiki)

- netlist of statements (process without explicit sensitivity)?

[HWT](https://github.com/Nic30/hwt)

- netlist of statements

[magma](https://github.com/phanrahan/magma)

- netlist of statements

[MyHDL](https://github.com/myhdl/myhdl)

- processes

[SpinalHDL](https://github.com/SpinalHDL/SpinalHDL)

- netlist of statements

[Veriloggen](https://github.com/PyHDI/veriloggen)

- whole Verilog

[Yosys](https://github.com/YosysHQ/yosys)

- netlist of hw processes ?

Updates from https://github.com/SymbiFlow/ideas/issues/19#issuecomment-441382660 and https://github.com/SymbiFlow/ideas/issues/19#issuecomment-441619546