f4pga / f4pga/ideas

Create Python library for parsing / producing BLIF (and eBLIF) files

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help wanted project-symbiflow-arch-defs project-verilog-to-routing project-yosys type-coding
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Description

# Create a Python library for parsing / producing BLIF (and eBLIF) files

BLIF is the preferred method of design entry for many designers. The Berkeley Logic Interchange Format (BLIF) is a simple file format for exchanging sequential logic between programs.

eBLIF is an extension of the BLIF format to add features needed for using BLIF as part of an FPGA PnR flow created by Clifford Wolf. The best format is the [Verilog to Routing docs here](https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#extended-blif-eblif).

BLIF is used by Yosys, Arachne-pnr and Verilog to Routing.

There might be [a starting library here](https://github.com/whereyoufindthis/blifparse).

## Expected results

A Python library published on PyPi which makes it easy to read and write BLIF files.

# Knowledge Prerequisites

* Python

Contributor guide

No contributing guide indexed for this repository

Research direction

Start by reading the Verilog to Routing BLIF/eBLIF documentation and reviewing the referenced blifparse library. The issue names no repository files or tests, so the API and implementation scope need to be established before work begins. Done means a Python library is published on PyPI and can read and write BLIF files.

Written by the indexing model from the issue text.

Assessment

Tech stack
python
Domain
compilers
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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