f4pga / f4pga/ideas

Create a really good library for parsing / producing SDF files

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help wanted project-symbiflow-arch-defs project-verilog-to-routing type-coding
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Description

# Create a really good library for parsing / producing SDF files

[Standard Delay Format (SDF) format](https://en.wikipedia.org/wiki/Standard_Delay_Format) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between Dynamic timing verification and Static timing analysis.

It has usually two sections: one for interconnect delays and the other for cell delays.

SDF format can be used for back-annotation as well as forward-annotation.

The SDF format version 2.1 is produced by [Verilog to Routing for post implementation timing analysis](https://docs.verilogtorouting.org/en/latest/tutorials/timing_simulation/). It is also used by a lot of other EDA tools.

## Expected results

A Python library published on PyPi which makes it easy to read and write SDF files.

## Further reading

* [More information here.](http://vlsi.pro/standard-delay-format-sdf-file/)

# Knowledge Prerequisites

* Python

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