es-ude / es-ude/OnDeviceTraining

training_loop: non-sequential model topology — branch/merge DAG for forward+backward (epic)

Open
#329 0 comments 0 reactions 0 assignees View on GitHub
enhancement
Dominant language
C
Stars
1
Forks
3
Avg merge
1d 1h
Merged PRs (30d)
8

Description

## Problem

The model is a flat array (`layer_t **model`); forward walks it in order, and backward is literally `CalculateGradsSequential.c`. Every architecture with a branch — ResNet-style skips, DenseNet-style dense blocks, transformer residuals (consumer issues below) — is structurally impossible today, **regardless of which kernels exist**. Note also the pipeline angle: the elastic-ai.creator IR is graph-shaped; the sequential C runtime is the limitation ir2c would inherit.

## What the epic must deliver

1. **Graph representation** — branch/merge (DAG) topology, keeping the flat array as the trivial degenerate case; existing sequential examples must not change.
2. **Forward execution** — topological order. The traversal is easy; the hard part is **buffer planning**: wire lifetimes are no longer strictly nested, so the current implicit reuse pattern breaks. On MCU this is the core problem.
3. **Backward execution** — reverse topological order with **gradient accumulation at fan-out points**: a tensor consumed by k branches receives the *sum* of k dx contributions. The fused CrossEntropy+Softmax backward shortcut must survive the generalization.
4. **Merge ops** —
- elementwise **Add** merge node (arithmetic/Add.h exists; needs the layer-level node + backward = fan-out distribution of dx),
- channel-dim **Concat** (new op; backward = dx slicing).
5. **Quantized merge semantics** — adding two SYM wires with *different scales* needs defined rescale-to-common-scale behavior through the executeOp funnel; concat of differently-scaled SYM wires likewise (requantize-to-common vs. per-slice scales). This is the genuinely novel design work and deserves its own design round.
6. **Serialization + optimizer enumeration** — serialize/deserialize and parameter collection (`calcTotalNumberOfStates` et al.) currently walk the array; they must walk the graph.

## Consumers

- #331 — ResNet-style skip connections (minimal consumer: Add-merge)
- #332 — DenseNet-style dense blocks (needs Concat)
- #333 — time-series transformer (residual adds inside blocks)

## Suggested slicing

PR1 graph representation + forward; PR2 backward with fan-out accumulation; PR3 Add-merge node (unblocks ResNet-1D); PR4 Concat (unblocks DenseNet); quantized-merge semantics as its own spec before PR3/PR4 touch SYM wires.

Contributor guide

Open the contributing guide

Research direction

Start with the flat model representation (`layer_t **model`) and `CalculateGradsSequential.c`; review how forward, backward, serialization, and parameter enumeration currently walk the array. Use the suggested PR slices to define graph execution, fan-out gradient accumulation, Add and Concat merges, and quantized merge semantics, with completion requiring the listed consumers to be supported without changing sequential examples.

Written by the indexing model from the issue text.

Assessment

Tech stack
c
Domain
embedded-iot, machine-learning
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
25/100

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