RISC-V SIMD support

When considering RISC-V Vector (RVV) support in RyuJIT, the vector-length-agnostic (VLA) design introduces a few differences from fixed-width architectures like x86 or arm64. Even when just using RVV internally to back existing Vector128 and Vector256 paths, there are a couple of hardware characteristics that might interact differently with the riscv64 backend.

First, RVV uses configuration parameters like SEW (selected element width, which sets data bit-width) and LMUL (length multiplier, which groups multiple physical registers together). Because LMUL dynamically combines physical registers based on the instruction context, the backend will have to manage these variable register sets rather than relying entirely on the usual fixed register classes or pairs.

Second, every RVV operation relies on the current SEW and LMUL state set by `vsetvli` instructions. To avoid emitting redundant configuration changes across basic blocks, the riscv64 code generator likely needs a tracking pass to keep tabs on the active hardware state.

Finally, standard .NET SIMD loops rely on explicit strip-mining and scalar tail-cleanup blocks, but RVV handles tail processing natively within the main loop using the vl (vector length) register. Stripping the fixed-width assumptions during the morph or lowering phases would allow the backend to generate native VLA loop structures instead of emulating fixed-width boundaries.

Refs:
https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-ba25a36-2026-08-04/src/unpriv/vector-common.adoc
https://camel-cdr.github.io/rvv-bench-results/articles/vector-utf.html
https://www.youtube.com/watch?v=mxMEUIFL4xg (slides https://drive.google.com/drive/folders/1txe6YXQyklWyn26YUaC5SqNQwuHrFHpj)

Start by reading the riscv64 backend and the existing Vector128 and Vector256 paths, then trace how morphing and lowering represent SIMD loops and how vsetvli state could be tracked across basic blocks. The issue provides no file or test names; done would mean agreed design and implementation of RVV register handling, configuration tracking, and native VLA tail processing.

Written by the indexing model from the issue text.