[Core/Telemetry] Inject Inline Hardware Prefetch Primitives inside internal/storage/buffer_pool.go to Optimize L1 Cache lines

Commercial Production Objective

Enforce proactive data ingestion inside our allocation structures, allowing our active visual HUD dashboard (https://vercel.app) to render millions of live multi-tenant stream nodes with absolute 0ms rendering delay .

Bare-Metal Technical Specifications

1. Proactive Memory Prefetching: Inside our lock-free buffer allocator inside internal/storage/buffer_pool.go, embed direct hardware-level prefetch instructions (_mm_prefetch) to explicitly preload upcoming unsafe pointers index records onto active L1 processor cache lines .
2. Eliminating Cache Misses: Ensure that when parallel worker threads invoke data-plane redirection parameters, the telemetric pointer matrices are already physically present inside the nearest silicon registers, avoiding system RAM read cycles entirely .
3. Absolute Coherency Control: Prevents false sharing and cross-socket cache invalidation signals down to pure physical atomic boundaries .

Start by reading internal/storage/buffer_pool.go to understand the allocator and the access patterns this request targets. Define measurable cache or throughput improvements and platform constraints before attempting hardware prefetching; done requires evidence of improvement and no regressions, but the issue currently names no tests or acceptance criteria.