Regex Not Recognizing Windows Path Format for Verilog

## Information

**VIM version**

Vim8.2.12 or Neovim0.5.0

Operating System: Windows10

## What went wrong

Verilog regex to match the linter information is always wrong when it's on Windows since it has a different path.
For example, in iverilog.vim we have
" tb_me_top.v:17: error: Invalid module instantiation
**let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?'**
however, on windows we get error like:
**C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:41: syntax error**
The path includes **':'** so the regex can never match
I've checked for iverilog and vlog, they all have this kind of bugs. Guess it might be the same problem with all Verilog linter.
Actually there used to be these same issues:
- [Linter running but errors not showing · Issue #3340 · dense-analysis/ale](https://github.com/dense-analysis/ale/issues/3340)
- [Fix ghdl and vcom linter regex patterns to support Windows paths (i.e. drive letter and colon C:) by azvanderpas · Pull Request #3346 · dense-analysis/ale](https://github.com/dense-analysis/ale/pull/3346)

But it hasn't been solved yet.

## Reproducing the bug

1. Use iverilog or other verilog linter for ALE
2. Then because of the regex never match, so the errors never show up.

### :ALEInfo

Current Filetype: verilog
Available Linters: ['hdl-checker', 'iverilog', 'verilator', 'vlog', 'xvlog', 'yosys']
Enabled Linters: ['iverilog']
Ignored Linters: []
Suggested Fixers:
'remove_trailing_lines' - Remove all blank lines at the end of a file.
'trim_whitespace' - Remove all trailing whitespace characters at the end of every line.
Linter Variables:

let g:ale_verilog_iverilog_options = ''
Global Variables:

let g:ale_cache_executable_check_failures = v:null
let g:ale_change_sign_column_color = 0
let g:ale_command_wrapper = ''
let g:ale_completion_delay = v:null
let g:ale_completion_enabled = 0
let g:ale_completion_max_suggestions = v:null
let g:ale_disable_lsp = 0
let g:ale_echo_cursor = 1
let g:ale_echo_msg_error_str = 'Error'
let g:ale_echo_msg_format = '%code: %%s'
let g:ale_echo_msg_info_str = 'Info'
let g:ale_echo_msg_warning_str = 'Warning'
let g:ale_enabled = 1
let g:ale_fix_on_save = 0
let g:ale_fixers = {}
let g:ale_history_enabled = 1
let g:ale_history_log_output = 1
let g:ale_keep_list_window_open = 0
let g:ale_lint_delay = 200
let g:ale_lint_on_enter = 1
let g:ale_lint_on_filetype_changed = 1
let g:ale_lint_on_insert_leave = 1
let g:ale_lint_on_save = 1
let g:ale_lint_on_text_changed = 'normal'
let g:ale_linter_aliases = {}
let g:ale_linters = {'verilog': ['iverilog']}
let g:ale_linters_explicit = 0
let g:ale_linters_ignore = {}
let g:ale_list_vertical = 0
let g:ale_list_window_size = 10
let g:ale_loclist_msg_format = '%code: %%s'
let g:ale_max_buffer_history_size = 20
let g:ale_max_signs = -1
let g:ale_maximum_file_size = v:null
let g:ale_open_list = 0
let g:ale_pattern_options = v:null
let g:ale_pattern_options_enabled = v:null
let g:ale_root = {}
let g:ale_set_balloons = 1
let g:ale_set_highlights = 1
let g:ale_set_loclist = 0
let g:ale_set_quickfix = 1
let g:ale_set_signs = 1
let g:ale_sign_column_always = 1
let g:ale_sign_error = '>>'
let g:ale_sign_info = '--'
let g:ale_sign_offset = 1000000
let g:ale_sign_style_error = '>>'
let g:ale_sign_style_warning = '--'
let g:ale_sign_warning = '--'
let g:ale_sign_highlight_linenrs = 0
let g:ale_statusline_format = v:null
let g:ale_type_map = {}
let g:ale_use_global_executables = v:null
let g:ale_virtualtext_cursor = 0
let g:ale_warn_about_trailing_blank_lines = 1
let g:ale_warn_about_trailing_whitespace = 1
Command History:

(executable check - success) iverilog
(finished - exit code 2) 'cmd /s/c "iverilog -t null -Wall C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v"'

<<>>
C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v:225: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v:228: `elsif without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v:229: `endif without a matching `ifdef - ignored.
C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v:240: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIA6D9E.tmp\PipelineMIPS.v:236: syntax error
I give up.
<<>>

(finished - exit code 4) 'cmd /s/c "iverilog -t null -Wall C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v"'

<<>>
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:41: syntax error
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:41: error: invalid module item.
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:225: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:228: `elsif without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:229: `endif without a matching `ifdef - ignored.
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:240: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIB563A.tmp\PipelineMIPS.v:236: syntax error
I give up.
<<>>

(finished - exit code 4) 'cmd /s/c "iverilog -t null -Wall C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v"'

<<>>
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:41: syntax error
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:41: error: invalid module item.
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:225: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:228: `elsif without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:229: `endif without a matching `ifdef - ignored.
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:240: `ifdef without a macro name - ignored.
C:\Users\Honk\AppData\Local\Temp\VIC5800.tmp\PipelineMIPS.v:236: syntax error
I give up.
<<>>