[REQUEST] XPU: register native pinned host memory with the device runtime (follow-up to #8283)

Is your feature request related to a problem? Please describe.

#8283 taught the native pinned-memory allocator (DS_PIN_MEMORY_BACKEND=native, posix_memalign + mlock) to register host memory with the device runtime so that copy_(..., non_blocking=True) can go through the DMA engine. On CUDA this closed a large bandwidth gap (H200: ~10-17 GB/s with mlock only vs. ~53-55 GB/s after cudaHostRegister).

Registration goes through the new register_host_memory / unregister_host_memory accelerator hooks, but only CUDA_Accelerator overrides them. XPU_Accelerator inherits the base-class no-op, so on Intel GPUs native pinned buffers stay mlock-only and H2D/D2H transfers run at pageable bandwidth even with DS_PIN_MEMORY_REGISTER_DEVICE=1. The degradation is silent: registration just returns False and nothing logs.

Describe the solution you'd like

• Implement register_host_memory / unregister_host_memory in accelerator/xpu_accelerator.py, e.g. via Level Zero zeMemRegisterHostMemory / zeMemUnregisterMemory on the allocation range, honoring the same DS_PIN_MEMORY_REGISTER_DEVICE opt-out and the graceful "log once and continue with mlock" fallback on failure.
• Extend tests/unit/v1/pin_memory/test_pin_memory.py with an XPU equivalent of the CUDA cudart-mock test.
• Optionally extend benchmarks/pin_memory/h2d_d2h_bench.py so the before/after H2D/D2H bandwidth can be quantified on XPU.

Describe alternatives you've considered

• Keep mlock-only on XPU (status quo): functionally correct, but leaves H2D/D2H at pageable speeds for native-pin users on Intel GPUs.

Additional context

• Hooks added in #8283: no-op defaults in accelerator/abstract_accelerator.py, CUDA implementation in accelerator/cuda_accelerator.py (torch.cuda.cudart().cudaHostRegister / cudaHostUnregister).
• Call sites: NativePinnedMemory.pin / _release in deepspeed/utils/pin_memory.py.