Rewrite `axi-stream-s2` protocols to use `repeat` loops and run them through interpreter

The purpose of this is to see whether the interpreter can reveal the bug between `s2_buggy.prot` and `s2_fixed.prot`.

Note: this may require seeing whether the Verilog file from the Brave New World artifact works with our simulator (Kevin mentioned he tried running our interpreter directly but it didn't work out of the box as some pin names in the `.prot` file don't match the names in the Verilog file).