[Sisyphus] phase-2 / zcc / Wave 8 — ARM64 (AArch64) codegen

## Scope
Lower the optimized IR to AArch64 machine code, targeting the AAPCS64 ABI.

## Deliverables
- `phase2/zcc/src/codegen_arm64.zig` — instruction selection and lowering.
- `phase2/zcc/src/abi_arm64.zig` — AAPCS64 ABI rules (X0–X7 argument registers, stack alignment, leaf optimization).

## Coverage
- Same IR constructs as x86_64 (integer, FP, memory, control flow, function calls).
- Atomics: LL/SC (`ldxr`/`stxr`) or LSE (`cas`, `swp`, `ldadd`) when available.

## Success Criteria
1. Produce golden ASM for `001..023` at `-O0`; diffs are stable across runs.
2. Cross-assemble and cross-link; execute under `qemu-aarch64` in Docker.
3. Output matches gcc-built reference behavior (stdout, exit code).

## Dependencies on Prior Waves
- **Wave 0–7** — x86_64 codegen establishes the codegen framework; ARM64 reuses `asm.zig` and pass manager.

## Suggested Role Assignment
`arm64-codegen-engineer`

## Test Corpus Expectations
- Golden ASM snapshots for `001..023` at `-O0`.
- `qemu-aarch64` execution tests in CI Docker.

Start by reading the existing x86_64 codegen, phase2/zcc/src/codegen_arm64.zig, phase2/zcc/src/abi_arm64.zig, asm.zig, and the pass manager to understand the reusable framework. Run the existing 001..023 corpus and inspect its golden ASM and CI Docker setup. Done means stable -O0 AArch64 snapshots, successful cross-assembly and linking, qemu-aarch64 execution, and behavior matching gcc references.

Written by the indexing model from the issue text.