[Sisyphus] phase-2 / zcc / Wave 7 — x86_64 codegen

## Scope
Lower the optimized IR to x86_64 machine code, targeting the SysV AMD64 ABI.

## Deliverables
- `phase2/zcc/src/codegen_x86_64.zig` — instruction selection and lowering.
- `phase2/zcc/src/asm.zig` — assembly printer (GAS syntax) or direct ELF object emission.
- `phase2/zcc/src/abi_x86_64.zig` — SysV AMD64 ABI rules (argument passing in registers, stack alignment, red zone).

## Coverage
- Integer and floating-point arithmetic.
- Memory operations (load, store, alloca → stack slots).
- Control flow (branches, loops, switch lowered to jump table or binary search).
- Function prologue/epilogue, caller/callee-saved registers.
- Atomics: `LOCK` prefix for integer ops, `cmpxchg` for compare-exchange.

## Success Criteria
1. Produce golden ASM for `001..023` at `-O0`; diffs are stable across runs.
2. Assemble and link the output; resulting binaries execute and match gcc-built reference outputs.
3. macOS and Linux both supported (differences in leading-underscore and section names handled).

## Dependencies on Prior Waves
- **Wave 0–6** — optimized IR is the input to codegen.

## Suggested Role Assignment
`x86_64-codegen-engineer`

## Test Corpus Expectations
- Golden ASM snapshots for `001..023` at `-O0`.
- Execution tests: compile with `zcc`, link with system `ld`, run; compare stdout/exit-code against gcc-built binary.

Start by reading phase2/zcc/src/codegen_x86_64.zig, phase2/zcc/src/asm.zig, and phase2/zcc/src/abi_x86_64.zig, then trace how optimized IR from Waves 0–6 reaches code generation. Use the 001..023 golden ASM corpus and execution tests as the validation entry points. Done means stable -O0 assembly, linked binaries matching gcc references, and working macOS and Linux output.

Written by the indexing model from the issue text.