Add wishbone fifo's

Add the following circuits:

```haskell
-- | Wishbone to Df source
--
-- * Writing to the given address, pushes an item onto the fifo
-- * Reading always returns zero
-- * Writing to other addresses are acknowledged, but ignored
-- * Asserts stall when the FIFO is full
wishboneSource ::
-- | Address to respond to
BitVector addressWidth ->
-- | Depth of the FIFO
SNat depth
-- |
(Signal dom (WishboneM2S bytes), Signal dom Ack) ->
-- |
(Signal dom (WisboneS2M bytes addressWidth, Signal dom (Data (BitVector (8 * bytes)))

-- | Wishbone to Df sink
--
-- * Reading from the given address, pops an item from the fifo
-- * Writes are acknowledged, but ignored
-- * Reads from any other address are acknowledged, but the fifo element is not popped.
-- * Asserts stall when the FIFO is empty
wishboneSink ::
-- | Address to respond to
BitVector addressWidth ->
-- | Depth of the FIFO
SNat depth
-- |
(Signal dom (WishboneM2S bytes), Signal dom (Data (BitVector (8 * bytes))) ->
-- |
(Signal dom (WisboneS2M bytes addressWidth, Signal dom Ack)
```

Start by locating the repository's existing Wishbone and dataflow FIFO circuit entry points and their related tests. Compare their interfaces with the two signatures in this issue, then verify that the source and sink implement the stated address, read/write, acknowledge, and full/empty stall behavior.

Written by the indexing model from the issue text.