hardware: Computer Architecture course for timing/architecture/reversing/etc estimations

Freely available best one I am aware of, meaning having excellent overview, is https://safari.ethz.ch/architecture/fall2025/doku.php?id=schedule

• +1 has most general trade-offs besides internal computing bus design where I'd expect something along optimizing each phase of computing operations
• -1 very many trade-offs, lots of specialized tools

Interesting things I don't yet know about

• general full system simulation course (bus system with attached components), ie systemc/tlm for discrete systems, for hw/sw codesign
  • computing unit simulation (for stuff like side effects) needs cycle accuracy of internal bus (which is IP) and 10GHz oscillilsopes+X are expensive
  • hardware based CPU register loggers exist and likely related simulators (I guess all with redacted commit queue time in cycles)
• simulation standard(s) + libs for hardware bigger than bus systems
  • router/routing simulators based on routing configs by private cloud vendors with good timing accuracy exists, but not for private consumers
  • anything more complex with accurate timing is not open source, since data curation and handling itself becomes costly/IP (https://brianlinkletter.com/open-source-network-simulators/ also looks like simplified emulation tooling similar or simpler than systemc/tlm based simulations.)

Feel free to close, if not in scope or other focus.

No target file, test, or entry point is identified. Start by reviewing how this repository organizes learning resources, then assess whether the ETH Zürich computer architecture course fits the collection and whether the listed simulation topics need separate resources. Done means adding a clearly scoped resource entry or documenting why the suggestion is out of scope.