bytecodealliance / bytecodealliance/wasmtime

riscv64: Add Support For Linker Relaxation

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cranelift:area:riscv64
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Description

👋 Hey,

RISC-V has a number of linker relaxation optimizations that it can perform. These require the `R_RISCV_RELAX` relocation to be used in order for the linker to be able to apply them.

This is also a continuation of the discussion in #7047. There we decided that it would not be a good idea to implement compressed conditional branches due to their low offset range. We can instead implement them as normal branches and use `RELAX` to let the linker compress them if it finds it beneficial.

All of the possible relaxation sequences are available in the [Linker Relaxation](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#linker-relaxation) section of the RISC-V ELF document.

### Implementation

We can't just apply `RELAX` to the existing relocations and expect everything to work. Since cranelift has a similar `Label` mechanism that computes offsets, adding `RELAX` at any point in the middle of those would cause these offsets to become wrong.

The easiest way that I can think of to implement this would be to add a flag to cranelift that would preserve all labels that were emitted during lowering and transform all `LabelUse`'s into their equivalent relocation.

This would allow the linker to have knowledge of where all the branches are, and adjust them based on what relaxations it has performed.

Contributor guide

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