riscv64: Suboptimal register allocation for short function

👋 Hey,

This is something that I noticed while working on #7123.

### `.clif` Test Case

```
test compile precise-output
set unwind_info=false
target riscv64

function %c_lh(i64) -> i16, i16 {
block0(v0: i64):
v1 = load.i16 v0+0
v2 = load.i16 v0+2
return v1, v2
}

; VCode:
; block0:
; lh a3,0(a0)
; mv a4,a3
; lh a1,2(a0)
; mv a0,a4
; ret
;
; Disassembled:
; block0: ; offset 0x0
; lh a3, 0(a0)
; mv a4, a3
; lh a1, 2(a0)
; mv a0, a4
; ret
```

### Steps to Reproduce

* `clif-util test ./the-above`

### Expected Results

We could eliminate the first move by generating something along these lines:

```
; VCode:
; block0:
; lh a3,0(a0)
; lh a1,2(a0)
; mv a0,a3
; ret
```

### Actual Results

We get an extra move between loads.

### Versions and Environment

Cranelift version or commit: main

Operating system: Linux

Architecture: RISC-V

### Extra Info

VCode:
```python
VCode {
Entry block: 0
v193 := v196
v194 := v195
Block 0:
(original IR block: block0)
(instruction range: 0 .. 4)
Inst 0: args v192=a0
Inst 1: lh v196,0(v192)
Inst 2: lh v195,2(v192)
Inst 3: rets v193=a0 v194=a1
}
```