riscv64: Improve SIMD `ExtAddPairwise` Instruction Codegen

👋 Hey,

#### Feature

Currently we don't have any special lowerings for the `ExtAddPairwise` family of WASM instructions, so we generate a quite poor implementation.

#### Benefit

We can get better codegen on this backend for these instructions.

#### Implementation

[`cranelift-wasm` translates these](https://github.com/bytecodealliance/wasmtime/blob/77181024cade266d52ca8caaf412c1a4f9fcf261/cranelift/wasm/src/code_translator.rs#L2028-L2050) as `iadd_pairwise(uwiden_low(x), uwiden_high(y))` and similar variations.

We use the generic `iadd_pairwise` implementation which is quite large, however with the widening instructions as an input, we can generate much better codegen.

Since we know we are going to discard half of the input register elements, we can use a single `vrgather.vv` on each input to reshuffle them and then use a `vwadd.vv` to do the sum.

This is pretty much what [v8 emits for these instructions](https://github.com/v8/v8/blob/ad655dc0435b02f40b19dd9b091c2dcbc3aed5f2/src/compiler/backend/riscv/instruction-selector-riscv.h#L767-L772).

#### Alternatives

We don't need to do this, the current lowerings are working as intended. I also don't know how often these instructions get used in real code.