Perform I-Cache Maintenance on RISC-V

👋 Hey,

This is a follow up to a [discussion we recently had about I-Cache maintenance](https://github.com/bytecodealliance/wasmtime/pull/4997#discussion_r987218051). I'm filing this as a separate issue since I would prefer to deal with this in a different PR than that one.

That PR cleans up our interface for I-Cache maintenance in a way that's hopefully not too AArch64 specific. In the process we noticed that RISC-V does not perform any I-Cache maintenance actions, despite the architecture not guaranteeing that it is cache coherent.

For AArch64 we do a `CORE_SYNC` membarrier and a `clear_cache` (some asterisks here, see the PR discussion), but from my look at the [kernel docs](https://docs.kernel.org/riscv/features.html) it looks like `CORE_SYNC` is not yet available for RISC-V. They have a [custom syscall](https://github.com/torvalds/linux/blob/2bca25eaeba6190efbfcb38ed169bd7ee43b5aaf/arch/riscv/include/uapi/asm/unistd.h#L28-L45) that seems to do the all-core `clear_cache` part, but we should double check what other guarantees it provides us.