bytecodealliance / bytecodealliance/wasmtime

[cranelift] Avoid 64-bit imul_imm if possible on all architectures

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cranelift cranelift:area:machinst cranelift:goal:optimize-speed enhancement performance
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Description

#### Feature

Not all architectures has a fast 64-bit imul + imm. But even on modern like SnB-family and AMD Ryzen it takes `3 cycle` latency, `1c throughput` which not always faster lea + shl / add combination. So I propose use lowering to lea + shl / add for non-power of two constants ~~at least for `imm < 400`~~ with low hamming weight and 64-bit imul only if this possible. Similar to GCC:

https://godbolt.org/z/aG7bPer9v

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