[cranelift-codegen] Feature Request: Support for Rust-like Memory Ordering in Atomic IR Instructions in InstBuilder

#### Feature

Currently, Cranelift's atomic instructions (`atomic_load`, `atomic_store`, `atomic_rmw`, and `atomic_cas`) are hardcoded to **Sequentially Consistent (SeqCst)**.

Even though it is correct for the current WebAssembly Threads proposal, it results in a performance bottleneck for non-Wasm frontends like `rustc_codegen_cranelift` or custom JITs that might require C11-style weak memory ordering.

#### Proposed Change

Addition of a `MemoryOrdering` enum to the following:
- `atomic_load`
- `atomic_store`
- `atomic_rmw`
- `atomic_cas`

Suggested Ordering of enum

```rs
enum MemoryOrdering {
Relaxed,
Acquire,
Release,
AcqRel,
#[default]
SeqCst, // Default for backward compatibility
}
```

#### Implementation

- Updating the CDSL in cranelift-codegen/meta
- Updating ISLE

#### Alternatives

- **FFI/Libcalls:** High overhead due to context switching and defeats the purpose of MemoryOrdering.
- Inline Assembly: Brittle, defeats the purpose of a portable IR.

### Please Note

I am currently only focusing on the high level IR representation. I am not much acquainted with the spefic ISA lowering logic and hence, leave it to those more familiar than I am.