Cranelift: Tracking Issue: Missing ISLE lowering rules and internal panics

As suggested in #12171 , I am aggregating the missing lowering rules and internal errors I've encountered into a single tracking issue. I will update this list as I discover more cases.

### X86_64

- [ ] **`vany_ture` with `i8x16` args** (Panic: `no rule matched for term bitcast_gpr_to_xmm`)

Click to view reproduction (.clif)

```clif
function %main() -> i8 fast {

block0:
v4 = iconst.i8 -29
v23 = scalar_to_vector.i8x16 v4 ; v4 = -29
v49 = vany_true v23
return v49
}

; print: %main()

- [ ] **`sadd_sat` / `uadd_sat`/`usub_sat`/`ssub_sat` with `i64x2` / `i32x4` operands**

Click to view reproduction (.clif)

```clif
function %main() -> i64x2 fast {
const0 = 0x7fffffffffffffff04621ba7d10dbff0
block0:
v13 = vconst.i64x2 const0
v21 = sadd_sat.i64x2 v13, v13
return v21
}

; print: %main()

- [ ] **`uunarrow` with `i64x2` operands**

Click to view reproduction (.clif)

```clif
function %main() -> i32x4 {
const0 = 0x7e2ac3193c260db87e307092f0285f4c
block0:
v0 = vconst.f64x2 const0
v1 = fcvt_to_uint_sat.i64x2 v0
v2= vconst.i64x2 [1 1]
v3 = uunarrow v1, v2

jump block1

block1:
return v3
}

; print: %main()

### aarch64

- [ ] **`band_not` with `f64` args** (Panic: `thread 'main' panicked at cranelift/codegen/src/isa/aarch64/inst/emit.rs:97:5: assertion ``left == right`` failed`)

Click to view reproduction (.clif)

```clif
function %main() -> f64 fast {

block0:
v2 = f64const 0.0
v5 = iconst.i32 -428912370
v11 = f64const 0x1.fffffffffffffp1023
v22 = iconst.i32 0
v39 = band_not v11, v2 ; v11 = 0x1.fffffffffffffp1023, v2 = 0.0
return v39
}

; print: %main()

- [ ] **`vhigh_bits` with `f32x4` args** (Panic: ``should be implemented in ISLE: inst = `v2 = vhigh_bits.i64 v1 ; v1 = const0`, type = `Some(types::I64)``)``

Click to view reproduction (.clif)

```clif
function %main() -> i64 fast {
const0 = 0x0ad2e8b00a928acaf0edab5180000000
block0:
v1 = vconst.f32x4 const0
v2 = vhigh_bits.i64 v1
return v2
}

; print: %main()

### RISCV64

- [ ] **`select_spectre_guard` with `i8x16` args** (Panic: ``should be implemented in ISLE: inst = `v4 = select_spectre_guard.i8x16 v1, v2, v3`)``

Click to view reproduction (.clif)

```clif
function %main() -> i8x16 fast {
const0 = 0x00091ff3e51211e7f6fe0f1d04f71bf4
const1 = 0xe4f009ffe2e8f01ef5f0faf40401e014
block0:
v1 = iconst.i64 0x7fff_ffff_ffff_ffff
v2 = vconst.i8x16 const0
v3 = vconst.i8x16 const1
v4 = select_spectre_guard.i8x16 v1, v2, v3
return v4
}

; print: %main()

### S390x

- [ ] **`bxor` with `f32` and `f64` block args** (Panic: `no rule matched for term aluop_xor`)

Click to view reproduction (.clif)

```clif
function %main() -> f64 fast {

block0:
v10 = f32const -0x1.fffffep127
v11 = f64const 0x1.20365be59651ap996

v21 = bxor v11, v11 ; v11 = 0x1.20365be59651ap996, v11 = 0x1.20365be59651ap996
v65 = iconst.i32 0
return v21
}