Cranelift: run and compile commands on riscv64 backend fail

### `.clif` Test Case

```
test run
set opt_level=speed
set preserve_frame_pointers=true
set enable_multi_ret_implicit_sret=true

target riscv64 has_zcd has_zbkb has_zbc has_zbs has_zicond has_zvl32b has_zvl64b has_zvl128b has_zvl1024b has_zvl2048b has_zvl4096b has_zvl8192b has_zvl16384b has_zvl32768b
target x86_64 sse42 has_avx

function %main() -> i32x4 fast {
    ss0 = explicit_slot 32
    ss1 = explicit_slot 32
    const0 = 0x40ad3fb47cb16076c8cb1fdd8189d40f

block0():
    v1 = vconst.i32x4 const0
    v2 = bxor v1, v1
    v3 = icmp.i32x4 ne v1, v2
    return v3
}

; print: %main()
```

### Steps to Reproduce

On x86 `./clif-util run -v test1.clif` —— It runs correctly.

But when executed via `qemu-riscv64`, it reports an error.
```
test1.clif: The target ISA specified in the file is not compatible with the host ISA
1 file
Error: 1 failure
```

Similarly, for the `compile` command
```
/home/wasmtime/target/debug/clif-util compile --target=x86_64 test1.clif
```
This command runs as expected.
```
qemu-riscv64 -L /usr/riscv64-linux-gnu -E LD_LIBRARY_PATH=/usr/riscv64-linux-gnu/lib /home/wasmtime/target/riscv64gc-unknown-linux-gnu/release/clif-util compile --target=riscv64 test1.clif
```
However, on riscv64, returning a vector value consistently results in an error:
```
Error: Unsupported feature: Too many return values to fit in registers. Use a StructReturn argument instead. (#9510)
```

So, is this due to a mistake in how I'm using it, or is it a problem with the implementation?