AccuracyCoin: 32 remaining test failures

## AccuracyCoin Test Status

**102 passed, 32 failed, 0 not run** out of 134 tests.

Recent fix: Register Quirks (0x0482) is now passing and has been removed from known failures.

## Remaining Failures by Category

### CPU Interrupts (3 tests)
These require cycle-accurate interrupt handling — the emulator doesn't model the exact cycle at which interrupt flags are polled or how interrupts interact with concurrent instructions.

| Test | Error | Details |
|------|-------|---------|
| Interrupt flag latency | 0x06 (sub 1) | Need to poll IRQ/NMI at the correct cycle within each instruction |
| NMI Overlap BRK | 0x0A (sub 2) | NMI arriving during BRK should hijack the vector |
| NMI Overlap IRQ | 0x06 (sub 1) | NMI arriving during IRQ dispatch should take priority |

### DMA (9 tests)
DMA is handled atomically (all 256 bytes copied instantly). Real hardware interleaves DMA reads/writes with the CPU bus cycle-by-cycle, allowing PPU/APU register side effects during the transfer. Fixing these requires a major architectural change.

| Test | Error |
|------|-------|
| DMA + `$2002` Read | 0x0A |
| DMA + `$2007` Read | 0x0A |
| DMA + `$2007` Write | 0x06 |
| DMA + `$4015` Read | 0x0A |
| DMA + `$4016` Read | 0x06 |
| DMC DMA Bus Conflicts | 0x0A |
| DMC DMA + OAM DMA | 0x0A |
| Explicit DMA Abort | 0x0A |
| Implicit DMA Abort | 0x06 |

### APU (3 tests)

| Test | Error | Details |
|------|-------|---------|
| Frame Counter IRQ | 0x1E (sub 7) | 6 subtests pass; likely an edge case in frame counter IRQ timing after `$4017` write |
| Delta Modulation Channel | 0x12 (sub 4) | 3 subtests pass; specific DMC timing or register behavior |
| APU Register Activation | 0x06 (sub 1) | Fails on first subtest — likely initial register state or `$4015` enable/disable behavior |

### Controller (1 test)

| Test | Error | Details |
|------|-------|---------|
| Controller Strobing | 0x12 (sub 4) | 3 subtests pass; partial fix exists, one edge case remaining |

### PPU Behavior (2 tests)
These need dot-accurate PPU state during register reads.

| Test | Error | Details |
|------|-------|---------|
| Rendering Flag Behavior | 0x0A (sub 2) | How BG/sprite enable bits affect rendering mid-frame |
| `$2007` read w/ rendering | 0x06 (sub 1) | VRAM reads behave differently when rendering is active |

### Sprite Evaluation (8 tests)
All require rewriting the sprite evaluation pipeline to match the real hardware's per-scanline OAM evaluation algorithm (including its famous overflow bug).

| Test | Error |
|------|-------|
| Sprite overflow behavior | 0x06 |
| Sprite 0 Hit behavior | 0x06 |
| Suddenly Resize Sprite | 0x06 |
| Arbitrary Sprite zero | 0x06 |
| Misaligned OAM behavior | 0x06 |
| Address `$2004` behavior | 0x06 |
| OAM Corruption | 0x0A |
| INC `$4014` | 0x0E (sub 3) |

### PPU Misc (4 tests)
These need dot-accurate rendering with per-dot shift register emulation — the current scanline-at-a-time renderer can't model these behaviors.

| Test | Error |
|------|-------|
| Attributes As Tiles | 0x06 |
| Stale BG Shift Registers | 0x0E (sub 3) |
| BG Serial In | 0x0A |
| Sprites On Scanline 0 | 0x0A |

### CPU Behavior 2 (2 tests)

| Test | Error | Details |
|------|-------|---------|
| Instruction Timing | 0x0A (sub 2) | Need cycle-accurate instruction timing |
| Implied Dummy Reads | 0x0E (sub 3) | Blocked by DMA sync prerequisite |

## Estimated Difficulty

**Easiest to fix (targeted, small changes):**
1. **Controller Strobing** — 3/4 subtests pass, small codebase (`controller.js`)
2. **APU Register Activation** — fails on sub 1, likely a specific register behavior
3. **Frame Counter IRQ** — 6/7 subtests pass, one edge case
4. **Delta Modulation Channel** — 3/4 subtests pass

**Medium (significant but contained work):**
5. CPU Interrupts (3 tests) — need cycle-accurate interrupt polling
6. Instruction Timing — need per-instruction cycle count fixes

**Hardest (architectural changes):**
7. DMA (9 tests) — requires cycle-level bus emulation instead of atomic DMA
8. Sprite Evaluation (8 tests) — requires rewriting OAM evaluation pipeline
9. PPU Misc (4 tests) — requires dot-level rendering pipeline
10. PPU Behavior (2 tests) — requires dot-accurate PPU state