SPI library does not limit the maximum SPI clock frequency as per the datasheet

While the current SPI.h tries to safe-limit the maximum SPI clock frequency of the SAMD core, it does so in a weird way, assuming F_CPU to be always 48000000L and only for the SAMD21G18A part.
https://github.com/arduino/ArduinoCore-samd/blob/master/libraries/SPI/SPI.h

This has two problems,
- Will fail for the SAMD21G18A if F_CPU takes a different value.
- Will fail for any other SAMD21 parts, as the code relaxes lowers in this case the value of SPI_MIN_CLOCK_DIVIDER to 2.

A comment in the code also states that the maximum SPI clock frequency is not specified in the datasheet. However, it is. According to the datasheet for the SAM D21E, D21G and SAM D21J ("Atmel-42181I-SAM L21_Datasheet_Complete-03/2016"), page 997,
- tSCK SCK period in master mode is typically 84ns, which roughly translates into 11.9MHz.
- According to Atmel, the value above is based on simulation. It is not tested in production.

I have prepared a patch for correcting SPI.h so that it effectively limits the max SPI clock frequency to 12000000L, for all F_CPU values and all SAMD21 parts. Is it OK if I submit a pull request?

Start in libraries/SPI/SPI.h and inspect the existing SAMD21G18A and F_CPU-based clock-divider logic. Compare it with the SAM D21E, D21G and D21J datasheet entry on page 997. Done means the maximum SPI clock is limited to 12000000L for every F_CPU value and all SAMD21 parts.

Written by the indexing model from the issue text.