Wire does not configure the I2C mode SCI pins correctly

It appears the Wire library only configures the I2C SDA/SCL pins in CMOS mode when a SCI port is selected

https://github.com/arduino/ArduinoCore-renesas/blob/99f8ee40613b165de124471d9a2b15bf5e2057fb/libraries/Wire/Wire.cpp#L255-L256

The pin mode flags should probably read:

`(uint32_t) (IOPORT_CFG_PULLUP_ENABLE | IOPORT_CFG_PERIPHERAL_PIN | IOPORT_CFG_NMOS_ENABLE | ioport_sda)`

To activate the pins in open drain mode rather than CMOS mode.

I'm actually not sure if this doesn't affect the standard IIC module too, as far as I know the pin mode configuration process that would be used in the FSP is the same. I would have thought someone would have noticed a poor performing IIC port by now. For now I have identified it on my XIAO RA4M1 on the No. 2 I2C channel (D6 and D7 on that kit), after chasing erratic communications down with an oscilloscope. The nature is that the runt pulses sometimes do pass the data so it appears as though the communications is only erratic.

Start in libraries/Wire/Wire.cpp at the cited pin configuration around lines 255-256, then compare the SCI and standard IIC setup paths. Reproduce the erratic communication on the XIAO RA4M1 I2C channel 2 pins D6/D7 and inspect the signals with an oscilloscope. Done means both relevant paths configure SDA/SCL for open-drain operation without runt pulses.

Written by the indexing model from the issue text.