This implementation conflicts with SMBus specification

Today I ran into an issue while implementing a PMBus interface on an Arduino every.
PMBus derrives from SMBus which uses I2C and ultimately TWI.

From System Management Bus Specification Version 3.3:


This requires a 0 byte read or write transaction where the read is currently not possible with this implementation as the write bit is implicitly set in both cases.

Both cases result in a call to
```
uint8_t TWI_MasterWriteRead(uint8_t slave_address,
uint8_t *write_data,
uint8_t bytes_to_write,
uint8_t bytes_to_read,
uint8_t send_stop)
```
with bytes_to_write and bytes_to_read both being 0.

In this case the function always sets the write bit:

```
else if (master_bytesToWrite == 0 && master_bytesToRead == 0) {
twi_mode = TWI_MODE_MASTER_TRANSMIT;
uint8_t writeAddress = ADD_WRITE_BIT(master_slaveAddress);
TWI0.MADDR = writeAddress;
}
```

Am I missing something here? Or did somebody want to save a few lines, not having this special case in mind?

https://github.com/arduino/ArduinoCore-megaavr/blob/5e639ee40afa693354d3d056ba7fb795a8948c11/libraries/Wire/src/utility/twi.c#L322

Start in libraries/Wire/src/utility/twi.c around the referenced TWI_MasterWriteRead implementation and inspect the zero-byte branch. Compare its address-bit handling with the SMBus 3.3 requirement for zero-byte read and write transactions. Done means the relevant transaction types follow the specification without regressing existing Wire behavior.

Written by the indexing model from the issue text.