Wire lib uses alot of RAM memory by design (no error)

Hi,
I want to provide a change to the wire buffer management. Basicly it works fine but it needs a lot of ram memory. I took the core wire communication part and modified it for the bus master part. As a result my implementation uses much less memory. Please take a look at my lib, you can find it under https://github.com/andreobi/Jeti_ExBusSensor ao_WireLight. Perhabs it might be interesting for you. I also made a change to the interrupt handling: other interrups are allowed, when the client requests a bus wait.

Andre

Compare the core Wire communication and buffer-management implementation with the external ao_WireLight library linked in the issue. Review how its reduced memory use and interrupt handling behave, then define completion as an agreed implementation or documented decision for the AVR core.

Written by the indexing model from the issue text.