Wrong ADC Prescaler Calculation

Wrong ADC Prescaler Calculation in AVR wiring.c
```
#elif F_CPU >= 8000000 // 8 MHz / 64 = 125 KHz
sbi(ADCSRA, ADPS2);
sbi(ADCSRA, ADPS1);
cbi(ADCSRA, ADPS0);
#elif F_CPU >= 4000000 // 4 MHz / 32 = 125 KHz
sbi(ADCSRA, ADPS2);
cbi(ADCSRA, ADPS1);
sbi(ADCSRA, ADPS0);
```
If F_CPU=7372800 (baudrate crystal)
The prescaler ist set to DIV_32
7372800/32=230400 Hz
230kHz is too much
between 200 and 50 are fine values

Start in wiring.c at the F_CPU prescaler branches shown in the issue. Check the selected divider and resulting ADC clock for 7,372,800 Hz, then verify the relevant frequency cases keep the ADC clock between 50 and 200 kHz. Done means the baud-rate crystal case no longer selects a value above that range.

Written by the indexing model from the issue text.