Basic IP Cores requirement for NuttX for Zybo Z7 or any FPGA

Dear @btashton,

What are the IP cores should be added in Zybo Z7 platform which is already written in litex-boards( https://github.com/litex-hub/litex-boards)

Does generating the bitstream with a UART and VexRISC-V core (which has D-cache and I-cache) suffice for booting NuttX.
(i am asking this because the Arty A7 build has extra IP Cores such as LiteDRAM,LiteEthernet etc..)

with the existing platform in litex-boards for Zybo Z7 and doing make menuconfig on SW side would hopefully work right ?