acmpesuecc / acmpesuecc/aes-128-sysverilog-riscv

Testbench required for round.sv

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#6 7 comments 0 reactions 0 assignees View on GitHub
Bounty: 25 documentation enhancement
Dominant language
SystemVerilog
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1
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No merged PRs in 30d

Description

# Description
Add a testbench for `round.sv` to validate it's functionality. Please refer to [this](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) for a tutorial on writing a testbench.

# Notes:
- You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

Contributor guide

Open the contributing guide

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