Testbench required for aes_cip.sv

# Description
Add a testbench for `aes_cip.sv` to validate it's functionality. Please refer to [this](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) for a tutorial on writing a testbench.

# Note:
- You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.