Testbench required: Implement a testbench for syncRAM.sv

## Description
Write a testbench code for the syncRAM.sv. Make sure to attach the RTL simulation file if possible

## Understanding code
Make sure to clone the repo and compile the syncRAM.sv once to check if it is working before writing the testbench.

## Resources
Refer to this [link](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) to learn more about writing a testbench.

**Bounty points allotted: 100+**

If you face any issues or have any queries, do not hesitate to contact the maintainers. Happy contributing!