Testbench required: Implement a testbench for an accepted PR for #1

## Description
Write a testbench for the SystemVerilog code that is accepted in issue #1. Make sure to test it with RTL simulation and verify with the code from the issue.

## Understanding code
Make sure to fork and clone the accepted PR from #1 and compile the .sv file once to check if it is working before writing the testbench.

## Resources
Refer to this [link](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) to learn more about writing a testbench.

**Bounty points allotted: 60+**

If you face any issues or have any queries, do not hesitate to contact the maintainers. Happy contributing!