acmpesuecc / acmpesuecc/BareBones
Design a circuit based on these requirements - 1
- Lenguaje dominante
- SystemVerilog
- Estrellas
- 3
- Forks
- 4
- Métricas de merge de PR
- Sin PR fusionados en 30 d
Descripción
## Description
The client requires a circuit to be designed to fit these particular requirements:
Refer to this document for the truth table: [DAC-1.docx](https://github.com/suhaskv1/BareBones/files/7321066/DAC-1.docx)
## Understanding code
Things to keep in mind
1) Use dataflow style of coding.
2) Give more descriptive and appropriate variable names like input1, output1 and so on.
3) Remember to use comments to explain your code if you think it is necessary.
4) Make sure your final output RTL viewer should match the one given in the document.
5) Make a new file in the SystemVerilog directory.
## Resources
Refer to this [link](https://www.chipverify.com/systemverilog/systemverilog-tutorial) to learn more about writing a SystemVerilog code.
**Bounty points allotted: 60+**
If you face any issues or have any queries, do not hesitate to contact the maintainers. Happy contributing!
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