Use an existing standard for start/stop/reset MMIO control registers

Right now, the MMIO interface expected by the software layers consists of a control register at address 0 with reset/stop/start and a status register with done/busy/idle at address 4, followed by a generic 64-bit result register. But we never really put any more thought into this other than just putting in there what we needed at the time. We should probably do that before we converge to 0.1.

One standard we could for instance use is Xilinx's [SDAccel kernel memory map](https://github.com/Xilinx/SDAccel-Tutorials/blob/master/docs/getting-started-rtl-kernels/README.md#hardware-interface-requirements). It's already almost exactly like ours, except SDAccel passes all results through shared memory or streams and thus doesn't have a result register. We could just put that at 0x10/0x14 though. I think interrupts can be omitted, but we might want to add those at some point anyway. The advantage of using this interface is that we can more easily target Alveo boards with SDAccel flow in the future.