Integration in behavioral/RTL simulation through Vivado

Hello.

I have been using LibSystemCTLM-SoC to cosimulate my Zynq designs for behavioral/RTL simulations.

I use generated simulation scripts and files from Vivado and replace the "processing_system7_0_0" entity during elaboration (which normally is the Zynq Verification IP) by a custom made generic Zynq wrapper built around LibSystemCTLM-SoC and the TLM bridges.
This allows me to CoSimulate the entire system with QuestaSim and QEMU.
This required however to create several wrappers and scripts, especially to get all the parameters for the Zynq processing system (which ports are enabled, what are the width of the AXI ports etc.) as well as the creation of a specific SystemC Zynq model to instantiate all the ports to communicate with QEMU through remote port and convert the TLM transactions to AXI (Master/Slave) using the TLM bridges from LibSystemCTLM-SoC.

This works well but results in a rather large extra set of files and relies on home-made scripts (which will extract the parameters automatically from the IP files etc.). to configure everything.

It seems there could be some support in Vivado for automating this, but I could not find any documentation.
In a Vivado project with a Zynq PS there are the following files under :
project/project.srcs/sources_1/bd/block_design_name_bd/ip/block_design_name_bd_processing_system7_0_0/sim/

• block_design_name_bd_processing_system7_0_0.sv
• block_design_name_bd_processing_system7_0_0.v
• libremoteport.so

So there seems to be a SystemVerilog entity which uses Remote Port and TLM through the DPI.
Can this entity be used for co-simulation in any way ? Is there any documentation ? libremoteport.so offers functions to synchronize with QEMU as well as read and write remote port commands (very similar to https://github.com/Xilinx/libsystemctlm-soc/blob/master/libremote-port/remote-port-tlm.cc) however I did not find any documentation as to how to set this up. Is there any ?

LibSystemCTLM-SoC provides everything to create a "drop-in" replacement for the Zynq PS VIP used in simulation under Vivado which would allow to CoSimulate everything, is there anything provided here by Xilinx to launch such a simulation ?

Thank you for your time.

Start with the Vivado-generated files under project/project.srcs/sources_1/bd/block_design_name_bd/ip/block_design_name_bd_processing_system7_0_0/sim/ and the libremote-port/remote-port-tlm.cc reference mentioned in the issue. Determine whether the SystemVerilog entity and libremoteport.so have a documented co-simulation setup with Vivado, QuestaSim, and QEMU; done would be either documented supported steps or a clear statement that this workflow is unsupported.