refdesign-sim demo fails on Error: SIGNALS:: Unable to connect top.pcie_bridge.signals-master-tieoff_0.awvalid

Hello,
I'm trying to run the refdesign-sim demo, connecting to the Xilinx QEMU VM. The QEMU is running and waiting for connection:

(qemu) device_add remote-port-pci-adaptor,bus=rootport1,id=rp0
Failed to connect to 'machine-x86/qemu-rport-_machine_peripheral_rp0_rp': Connection refused
info: QEMU waiting for connection on: disconnected:unix:machine-x86/qemu-rport-_machine_peripheral_rp0_rp,server=on

The host is:
g++ --version g++ (Ubuntu 11.3.0-1ubuntu1~22.04.1) 11.3.0

 > verilator --version
Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad

SystemC 2.3.3

 > ldd tests/rtl-bridges/pcie/refdesign-sim
        linux-vdso.so.1 (0x00007ffd663da000)
        libsystemc-2.3.3.so => /lib/x86_64-linux-gnu/libsystemc-2.3.3.so (0x00007fc0d02df000)

I get a strange error when running refdesign-sim on the host:

> sudo ./refdesign-sim unix:machine-x86/qemu-rport-_machine_peripheral_rp0_rp 1000
        SystemC 2.3.3-Accellera --- Mar 17 2022 13:55:26
        Copyright (c) 1996-2018 by all Contributors,
        ALL RIGHTS RESERVED

Error: SIGNALS:: Unable to connect top.pcie_bridge.signals-master-tieoff_0.awvalid
In file: ../../test-modules/signals-common.h:97

After some debug it appears this is from this line: refdesign-sim.cc

108                         snprintf(pname, sizeof(pname) - 1, "m_axi_usr_%d_", bi);
109                         signals_m_tieoff[i].connect(ep_bridge, pname);

Where the verilated ep_bridge module (Vpcie_ep) seems to only return some generic port names for its child objects, which leads to this error.
For example, I print all child object names returned in the signal_find_child function, and the names are all of the form:
port_0
port_1
port_2
etc...

Looking at the Vpcie_ep.cpp/h files, and the module appears to have the correct SC ports, which should match with the refdesign-sim.cc code, if ep_bridge children returned the names of the SC module port variables.
Example: tests/rtl-bridges/pcie/obj_dir/Vpcie_ep.h, these should match the connections made in refdesign-sim.cc

   37     // PORTS
   38     // The application code writes and reads these signals to
   39     // propagate new values into/out from the Verilated model.
   40     sc_in<bool> clk;
   41     sc_in<bool> resetn;
   42     sc_out<bool> usr_resetn;
   43     sc_in<bool> s_axi_pcie_m0_awvalid;
   44     sc_out<bool> s_axi_pcie_m0_awready;
   45     sc_in<bool> s_axi_pcie_m0_wvalid;
   46     sc_out<bool> s_axi_pcie_m0_wready;
   47     sc_out<bool> s_axi_pcie_m0_bvalid;

Any ideas why the child names in ep_bridge are not matching, and seem to be generic port+number, such as 'port_0' etc..?

Start with tests/rtl-bridges/pcie/refdesign-sim.cc around the signals_m_tieoff connection, then inspect ../../test-modules/signals-common.h:97 and the generated tests/rtl-bridges/pcie/obj_dir/Vpcie_ep.cpp/.h files. Reproduce the refdesign-sim QEMU connection and determine why child ports are exposed as port_N names; done means the expected signal connections resolve without the SIGNALS error.