board-dependent code in SPD read of ZynqMP FSBL

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Assessment

Difficulty
3/5
Estimated time
1-2 days
Newbie friendliness
35/100
Issue type
Bug
Clarity
Mostly clear
Activity status
Stale
Tech stack
c
Domain
embedded-iot

Research direction

Start with lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c at lines 6627-6665 and inspect how the dynamic DDR initialization reads SPD data. Identify the conditional compilation used for Xilinx evaluation boards, then ensure the board-dependent I2C, mux address, and DIMM channel assumptions are guarded accordingly.

Written by the indexing model from the issue text.

Description

https://github.com/Xilinx/embeddedsw/blob/c12743e5d7b0140804699ea818cae66b8d7b62a5/lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c#L6627-L6665

Board-dependent code in dynamic DDR init section of ZynqMP FSBL, which assumes I2C1 is used, an I2C mux is present with a hard-coded device address and that the DIMM is assigned to a hard-coded channel number. This should be guarded by conditional compile for Xilinx eval boards.

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