Usage of L2-Cache in OpenAMP Scenarios
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Description
Referring to commit 6a07f5083531e4d755d675b3e3082fead153e5aa the use of L2 Cache is discouraged in Open AMP application since it can lead to unexpected behaviour as stated by @mubinsyed .
Based on that commit only the first section of the TLB is set to "inner cacheable", but not the entire L2-Cache. This seems to be inconsistent. I expected to have the whole DDR RAM being set to not cacheable or inner cacheable, but not only the first page.
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with commit 6a07f5083531e4d755d675b3e3082fead153e5aa and inspect the OpenAMP TLB setup described in the issue. Compare the first TLB section with the intended DDR RAM and L2-Cache treatment; done means the cacheability scope is made consistent with the documented OpenAMP expectation.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100