iic_v3_1

In XIic_DynMasterSend why are the XIIC_INTR_TX_ERROR_MASK and XIIC_INTR_TX_EMPTY_MASK interrupts cleared and enabled AFTER writing the address and data to the TX FIFO? When trying to talk to a slave in reset, I am expecting a NACK event to be generated. However, code based on the dynamic eeprom example is getting stuck waiting for TransmitComplete to zero out and the status handler never gets called with the NACK event.
I believe this happens because by the time the interrupts are cleared and enabled, the address in the FIFO is already sent and the TX Error Status bit is set. Clearing and enabling interrupt will lose the NACK event with no handlers called.

Start by reading XIic_DynMasterSend and the status handler, focusing on when the TX FIFO is written versus when XIIC_INTR_TX_ERROR_MASK and XIIC_INTR_TX_EMPTY_MASK are cleared and enabled. Reproduce the transfer with a slave held in reset and verify that the NACK event reaches the handler and TransmitComplete does not remain stuck.