Ethernet full-duplex communication issue with EMAC PS

When Ethernet full-duplex communication is performed (especially at high rates - over 1Gb Ethernet), it is noticed that Tx side of communication becomes the dominant one and completely "kills" the Rx side. This problem is already described at [1]. Emac PS Tx handlers are much more frequent while Rx side is overflowed with "Receive over run" errors from Emac PS error handlers. We assume that the same thing is causing problem described at [2]. Investigation on this problem would be appreciated.

Thank you,
Nenad

P.S. The problem was also noticed while using FreeRTOS+TCP network stack. Check at [3].

[1] - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-7000-LwIP-2-0-2-Low-RX-throughput-when-TX-is-active/m-p/870921
[2] - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/LwIP-Unresponsive-Tx-path-amp-TCP-MSS-effect/m-p/880420
[3] - https://sourceforge.net/p/freertos/discussion/382005/thread/3bde8d1d/

Begin with the EMAC PS Tx handlers and Rx error handlers while reproducing full-duplex traffic above 1 Gb Ethernet. Compare the behavior with the lwIP and FreeRTOS+TCP cases referenced in the issue. Done means identifying why Tx dominates and Rx overruns, with a documented reproducible conclusion or fix.