Cache incoherency issue in lwip with PS EMAC DMA driver
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Description
Initially posted on Xilinx forums [1]: there is DMA cache incoherencies when using lwIP and the PS EMAC on a Zynq at high throughput. The problem can be reproduced by following the steps in described in the post [1].
We have a workaround in place where we force lwIP to re-do IP packets checksum and invalidate any that fail. This obviously slows down the CPU and the total throughput but at least we can once again believe that the data we are receiving is valid. A fix would be appreciated however.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the reproduction steps in the linked Xilinx forum post and trace the lwIP and PS EMAC DMA path named in the issue. Done means received data is valid without forcing lwIP to redo packet checksums and invalidate failures, while avoiding the reported throughput loss.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, networking, performance
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100