IPlib: spi: possible invalid SPI FIFO read

In the following SPI RX FIFO consumption while-loop:

https://github.com/Xilinx/embeddedsw/blob/1bb19ac1ab06ab322ba4340bed372f93ca612a18/XilinxProcessorIPLib/drivers/spi/src/xspi.c#L746-L783

As this function does not mandate the parameter ByteCount to be divisible by {1, 2, 4}-byte. It is possible that the caller can pass something like 5-byte to transmit/receive. If this is the case, then, when ByteCount (remaining bytes to receive) is nearing zero, and the DataWidth is not of XSP_DATAWIDTH_BYTE, a read can potentially consumes invalid byte(s).

Instead, would it be more robust to do something like "always test the remaining bytes to receive, and switch to XSP_DATAWIDTH_BYTE when ByteCount is less than the preset DataWidth" ? Or, we should simply add a "divisible by {1, 2, 4}-byte" check at function prologue?

Start in XilinxProcessorIPLib/drivers/spi/src/xspi.c at the SPI RX FIFO consumption loop around lines 746-783, and trace how ByteCount and DataWidth behave for non-divisible sizes such as 5 bytes. Determine the intended handling for the remaining bytes, then verify that the FIFO is not read beyond the requested count.