Where is r0 set in SVC handler?
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Description
Hi there,
I noticed that in the SVCHandler you check r0 for the CPSR T bit.
Since control flow comes directly from the vector table, presumably r0 is still set to whatever the user code had stored in it, which could be some value other than CPSR.
Is it possible there is missing logic to load CPSR into r0 before line 115, e.g. ?
mrs r0, spsr
str r0, [sp, #-4]!
Could the current behavior cause issues if you had user code that sets r0 to an arbitrary value with the T bit set to a certain state, like this?
mov r0, #0x1234
svc #1
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Research direction
Start with lib/bsp/standalone/src/arm/cortexa9/armcc/asm_vectors.s around lines 113-119 and trace the vector-table path into SVCHandler. Check the ARM exception-state semantics for r0, CPSR, and SPSR, then reproduce the handler with an SVC caller that sets r0 to 0x1234. Done means confirming whether the T-bit check uses the intended state and documenting or correcting the behavior accordingly.
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Assessment
- Domain
- embedded-iot, operating-systems
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100