Incorrect validation of layer width
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Description
The validation of the layer width (not the logo layer) expects the layer window to be smaller than the hardware supports, while it should also allow exactly the hardware supported width (like for hight and for the logo layer width).
https://github.com/Xilinx/embeddedsw/blob/a8e6ff65ba32cef65062e9f3bd04e680fcb8d9bf/XilinxProcessorIPLib/drivers/v_mix/src/xv_mix_l2.c#L568
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Research direction
Start in XilinxProcessorIPLib/drivers/v_mix/src/xv_mix_l2.c around line 568, where the non-logo layer width is validated. Compare that check with the height and logo-layer width validation, then verify that the maximum hardware-supported width is accepted while smaller and larger values retain their intended behavior.
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Assessment
- Tech stack
- c
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Clearly specified
- Newbie friendliness
- 45/100