SPI multi byte transfer hangs in endless loop, when FIFOs are disabled

Dear Xilinx,

in xspi.c line 763:

  		DataLen = (InstancePtr->RemainingBytes > InstancePtr->FifosDepth) ?
  				InstancePtr->FifosDepth : InstancePtr->RemainingBytes;

This code alway returns 0, when there are still bytes to send, but the FIFOs are disabled (in hardware).
As a quick fix I changed the code to:

if ((InstancePtr->RemainingBytes > InstancePtr->FifosDepth) && (InstancePtr->FifosDepth != 0)) {
DataLen = InstancePtr->FifosDepth;
}
else {
DataLen =InstancePtr->RemainingBytes;
}

Best regards,
kmikl

Start in xspi.c around line 763 and trace the multi-byte transfer path when FIFOs are disabled. Verify that the transfer progresses when FIFO depth is zero, while the existing FIFO-enabled behavior remains correct, and confirm that the loop completes for data larger than one byte.