Xilinx / Xilinx/Vitis_Accel_Examples
Example file is missing.
Open
Nobody has claimed this yet.
- Dominant language
- Makefile
- Stars
- 605
- Forks
- 233
- Avg merge
- 1m
- Merged PRs (30d)
- 1
Description
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by checking the rtl_kernels/rtl_vadd example path and the reference to it in Getting_Started/Vitis/Part3.md. Verify which links are hanging and confirm that the referenced example or documentation target exists. Done means the example is available and the links resolve to the intended 2024.1 content.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 1/5
- Estimated time
- Under an hour
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100