Xilinx / Xilinx/Vitis_Accel_Examples

Enabling RAMA ip did not improve throughput in hbm_rama_ip demo

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Description

Use Vitis 2021.1 platform, XRT version is 2.11.634 and branch is 2021.1. Running hbm_rama_ip demo on the U50 platform, the results are as follows:
image

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Research direction

Start with the hbm_rama_ip demo on the U50 using the reported Vitis 2021.1 platform and XRT 2.11.634, and compare its throughput with RAMA enabled and disabled. The screenshot in the issue records the observed result; done means explaining or correcting why enabling RAMA does not improve throughput.

Written by the indexing model from the issue text.

Assessment

Domain
performance
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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